Nearly all microprocessor-based systems, especially those intended for general purpose computing, include one or more banks of random access memory for storage of programs and data. Typically, the central processing unit and the memory subsystem are interconnected by means of a multi-bit address bus and a separate multi-bit data bus. In addition, dedicated signals and interface circuitry are provided between the CPU and the memory subsystem to coordinate the exchange of data. The interface signals and the circuitry for processing them will vary depending upon the specifications of the microprocessor and the memory devices comprising the memory subsystem.
A popular microprocessor for use in general purpose computing systems is the 68030 microprocessor manufactured by Motorola. One of the signal inputs to this microprocessor for facilitating data exchange with memory subsystems and other peripheral units is a Data Strobe ACKnowledge, or DSACK* signal, which is active low. Throughout the following description, electrical signals that are active low (i.e., that are asserted by a low or near ground voltage) are denoted by appending the symbol "*". The 68030 actually has two data strobe acknowledge signals DSACK0* and DSACK1*. The clamp circuit of this invention can be used with either signal.
During data communications with peripheral units, the DSACK* signal is asserted by a peripheral unit to signify that data have been placed on the data bus. Since DSACK* outputs from many peripheral units may be associated with the CPU's DSACK* input, usually each peripheral DSACK* output consists of an open-drain pulldown driver that is normally maintained in an OFF state by the peripheral unit. All of the peripheral DSACK* outputs are connected together in a "wire-OR" configuration, and a separate resistor is used for the node's pullup.
Another DSACK* configuration has each peripheral unit actively driving its own separate DSACK* output signal. A logic OR gate then "sums" the signals to the 68030 microprocessor.
The manufacturer of the 68030 microprocessor specifies that DSACK* is asserted by driving the voltage on the input line to ground potential. The manufacturer further specifies that DSACK* must be deasserted (i.e. driven to a high state) after the deassertion of the CPU address strobe signal AS*. The maximum amount of time permitted from deassertion of AS* to deassertion of DSACK* varies with the CPU clock frequency of the 68030. However for a 40 MHz 68030 this specification is 25 nanoseconds.
If DSACK* is simply pulled high via a pullup resistor, the timing specifications of the chip manufacturer may not be met due to the delay caused by this resistor and circuit capacitance. Failure to meet the DSACK* timing specifications will adversely affect processor operation.
This problem has been addressed in the prior art by interface circuits that actively drive the DSACK* line high for a fixed period of time, after which the driver is placed in a high impedance state. However, DSACK* must not be actively maintained at a logical high state for any significant length of time since this would contribute to bus contention, noise and other problems. Prior art techniques for limiting the time that the DSACK* driver is actively in a high state include use of an open loop gate delay or a one clock period delay prior to returning to the high impedance state. These techniques cannot insure that DSACK* will be actively driven at a high state for a sufficient length of time to charge the line capacitance and still tri-state the DSACK* driver within the allowable specifications. A more desirable approach, and the one that is implemented by the present invention, is a feedback circuit for actively driving the DSACK* signal until the voltage exceeds a pre-defined "high" voltage, whereupon the driver is deactivated to a high impedance state.